SSS2301A p-channel enhancement mode mosfet product summary v ds (v) i d (a) -20v -2.3 a r ds(on ) ( m ? ) max 130 @v gs = -4.5v 190 @v gs = -2.5v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , march 2008 (rev 2.3 ) 1 absolute maximum ra tings (t a = 25 c unless otherwise noted) thermal characteristics parameter symbol limi t uni t o drain-source v oltage gate-source v oltage drain current-continuous @ t j = 25 c -pulse d drain-source diode forward current maximum power dissipatio n operating junction and storage t emperature range thermal resistance, junction-to-ambient o a a a b v ds v gs i d i dm i s p d t j , t stg r ja -2 0 v v a a a c/ w w c o o 8 - + -2.3 -8 -1.2 5 1.25 -55 to 150 100 so t- 23 d g s d g s fe at ures super high density cell design for low r ds(on ) . rugged and reliable. sot -23 package. pb free.
SSS2301A electrical characteristics (t a = 25 c unless otherwise noted) o uni t symbol parameter condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv dss i dss i gss v gs(th ) r ds(on) v gs =0v , i d =-250 a v ds =-16v , v gs =0v v gs = 8v , v ds =0v v ds =v gs i d =-250 a v gs =-4.5v , i d =-2.3a v gs =-2.5v , i d =-1.0a m v v a na -2 0 1 100 -1.0 130 190 -0.4 2 on-state drain current forward tr ansconductanc e tu rn-on delay ti me rise t im e tu rn-of f delay t im e fall ti me i d(on) g fs t d(on) t r t d(off) t f v ds =-5v , v gs =-4.5v v ds =-5v , i d =-2a v dd =-10 v, v gs =-4.5v , r l =10 -5 5 1 1 141 5 6 1 0 ns p f s a input capacitanc e output capacitanc e reverse t ransfer capacitance c is s c oss c rss v ds =-15v v gs =0v f=1.0mhz 355 7 8 37 to tal gate charge q g 3.5 i d =-1a, r gen =6 , nc -0.6 v -1.2 -0.8 0.5 1 v gs =0v , i d = -1 a i d =-2.3a, v gs =-4.5v v sd q gs q gd diode forward vo ltage gate-source charge gate-drain charge v ds =-10 v, notes a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2% . c. guaranteed by design, not subject to production testing. - - - south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , march 2008 (rev 2.3 ) 2
SSS2301A -v ds , drain-to-source v oltage (v ) - i d ) a ( t n e r r u c n i a r d , figure 1. output characteristic s -v gs , gate-to-source v oltage (v ) - i d t n e r r u c n i a r d , ) a ( figure 2. t ransfer characteristic s 0 0.2 0.4 0.6 0.8 1.0 1.2 10 8 6 4 2 0 - 5 5 c o 25 c o tj = 125 c o r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) -55 -25 0 25 50 75 100 125 2. 2 1. 8 1. 4 1.0 0.6 0.2 0 figure 4. on-resistance va riatio n with t emperatur e v gs = -4.5 v t j , junction te mpertature ( c) o i d = -2.3 a -v ds , drain-to-source v oltage (v ) ) f p ( e c n a t i c a p a c , c figure 3. capacitanc e 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 500 0 400 300 200 100 d e z i l a m r o n , h t v d l o h s e r h t e c r u o s - e t a g e g a t l o v tj , junction te mperature ( c ) figure 5. gate threshold va riatio n with t emperatur e o -50 -25 0 25 50 75 100 125 v ds = v gs i d = -250 a 1. 3 1. 2 1. 1 1. 0 0. 9 0. 8 0. 7 0 v b s s d d e z i l a m r o n , n w o d k a e r b e c r u o s - n i a r d e g a t l o v figure 6. breakdown vo ltage va riatio n with t emperatur e tj , junction te mperature ( c ) o -50 -25 0 25 50 75 100 125 1.15 1.10 1.05 1.0 0 0.9 5 0.9 0 0.85 i d = -250 a south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , march 2008 (rev 2.3 ) 3 0 0.5 1 1.5 2 2.5 3 10 8 6 4 2 0 - v gs = 4.5, 4, 3.5, 3, 2.5 - v gs = 1.5v - v gs = 2v
SSS2301A -i ds , drain-source current (a) g , s f ) s ( e c n a t c u d n o c s n a r t 0 5 10 15 20 2 5 figure 7. t ransconductance v ariation with drain current v ds = -5 v - i s ) a ( t n e r r u c n i a r d - e c r u o s , 20. 0 -v sd , body diode forward v oltage (v ) figure 8. body diode forward v oltage v ariation with source current 0.4 0.8 1.2 1.6 2.0 2.4 - v g s v ( e g a t l o v e c r u o s o t e t a g , ) figure 9. gate charge qg , t otal gate charge (nc) 0 0.5 1 1.5 2 2.5 3 3.5 4 5 4 3 2 1 0 v ds = -4.5v i d = -2.3a i d t n e r r u c n i a r d , ) a ( 0.01 -v sd , drain-to-source v oltage (v ) figure 10. maximum safe operating area 0.1 1 10 20 5 0 5 0 1 0 1 0.1 v gs = -4.5 v single pulse t c = 25 c o r d s ( o n ) l i m i t 9 7. 5 6 4. 5 3 1. 5 0 10. 0 0.0 t j = 25 c o 1 0 m s 1 0 0 m s 1 s d c 1.0 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , march 2008 (rev 2.3 ) 4
SSS2301A figure 11 . switching t est circuit v gs r ge n v ou t v dd v in d r l g s figure 12. switching wa veforms inver ted pulse width t r t d(on) v ou t v in t on t of f t d(of f) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized thermal tr ansient impedance curve t1 t2 p dm 1. r ja(t) = r(t)*r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0. 1 10 r f f e d e z i l a m r o n , ) t ( e v i t c e l a m r e h t t n e i s n a r t i m p e d a n c e duty cycle = 0. 5 square wa ve pulse duration (sec) 10 10 2 10 3 0. 2 0. 1 0.0. 5 0.02 0.01 single puls e south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , march 2008 (rev 2.3 ) 5
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